1. Field of the Invention
The present invention relates to high frequency data transfers. In particular, the present invention relates to a method and apparatus for reliably receiving synchronous data from a high frequency data source.
2. Description of the Related Art
Data movement within a computer system, for example, can take place in an asynchronous mode or in a synchronous mode. Asynchronous data transfers are accomplished by generating special control signals when data are provided on data lines. For example, in an asynchronous data transfer, a strobe signal may be provided when data are on the data lines, such that a sampling edge of the strobe signal (the edge to which the receiving module is responsive) coincides with steady data levels. Synchronous data transfers are accomplished by providing data to lines, such that steady data levels on the lines coincide with a sampling edge of the clock signal to which the data is synchronized. For example, the data may be synchronized to a system clock. During synchronous data transfers, steady-state or level data values are provided on the data lines coincident with the sampling edges of the system clock. The data are allowed to change (i.e., transition) only between adjacent clock sampling edges. Synchronous data operations generally result in data rates that are generally higher than those resulting from asynchronous data operations, especially with transfers of large amounts of data, because of the one-to-one correspondence between clock cycles and data cycles.
Synchronous Dynamic Random Access Memory (hereinafter xe2x80x9cSDRAMxe2x80x9d) is a generic name for various kinds of Dynamic Random Access Memory (hereinafter xe2x80x9cDRAMxe2x80x9d) that are synchronized with the system clock. Data operations employing SDRAMs generally comprise burst operations during which a special control signal is followed by a burst of data.
A by-product of the higher data rate is the reduction in access time that is allotted for each data read cycle or data write cycle. Data are read from or written to the memory module during a shorter time than that which is available in lower rate systems. For example, employing a 100 Mhz system clock, synchronous data that are read on a single edge of the system clock are at a steady state (not transitioning) for much less than 10 ns during a data cycle. During other times, the data are transitioning from a high level to a low level or from a low level to a high level. The sampling edge of the system clock used to read the synchronous data should generally coincide with steady state values of the data so as to capture valid data. Sampling during transitions of the data will generally result in uncertain data values that should not be used. Because of the very fast sampling rate, misalignment of the sampling edge of the system clock and the steady state data signal can result in sampling of data during clock transitions.
Although the clock and the data are synchronized, the sampling edge of the clock signal may occur substantially simultaneously with a data transition such that the clock may gate the state of the data before the transition, gate the state of the data after the transition, or gate an ambiguous state. The sampling edge of the clock signal may align with the data transition because delays in the circuit that generates the sampling clock signal may be different from delays in the circuit that provides the data. Printed circuit board traces have the effect of delaying a signal that is transmitted along the traces. Different length traces provide different delays. The delays are generally not long enough to have a significant effect on lower rate data transfers. Nonetheless, the delays attributed to different length traces may have a significant effect on high rate data transfers. A delay of as little as 2 nanoseconds on a high frequency data line can cause the relative shift of the data such that data transitions occur simultaneously with the sampling edge of the system clock signal. Thus, the outputs of the circuit which gates the data in synchronism with the system clock signal may not present the correct data. Since the outputs of this circuit comprise the data transferred to or from the SDRAM, erroneous data may be transferred. The relative shift of the data transitions in relation to the system clock signal is generally referred to as xe2x80x9cdata skewing.xe2x80x9d
Once data skewing becomes severe enough to cause unpredictable data behavior, the condition persists for an extended time interval. Because the data are driven by the same clock signal that is used to control the data sampling, the data transitions are separated by a multiple of clock signal cycles. Thus, once the data transition and a sampling edge of the system clock signal coincide, the next data transition also coincides with the sampling edge of the system clock signal. Therefore, there is a need for a method of reading data from an SDRAM while ensuring that data are correctly received, regardless of data skewing.
In accordance with the present invention, a receiving circuit receives synchronous data from data lines that are synchronized with a clock signal. The receiving circuit includes an over-sampling circuit. The over-sampling circuit samples the data during at least three time intervals in response to at least one edge of the clock signal. The samples from the module are provided to a decision circuit. The decision circuit determines the data levels provided on the data line by reference to the samples from the over-sampling circuit and by reference to the previous determinations of the decision circuit.
The present invention also provides a method of receiving synchronous data. The method first samples the data level of a data signal line at least three times in response to a sampling edge of a clock signal. The method then determines a least one data value based on the sampled levels and a previously determined data value.
In one embodiment the circuit of the invention is used to receive synchronous data from a data line. The data on the data line are synchronized with a clock signal. The circuit includes an over-sampling circuit, which provides data samples to a decision circuit, and which samples the data at least two times in response to at least one edge of the clock signal. The circuit also includes a decision circuit, which determines the data levels provided on the data line by reference to the samples from the over-sampling circuit and by reference to the previous level determined by the decision circuit.
The present invention further provides for a method of receiving synchronous data. The method includes a first step where the data level of a data signal line is sampled at least two times in response to a sampling edge of a clock signal. The method then continues with a step during which at least one data value is determined on the basis of sampled levels and a previous determination.